A Case For Asynchronous Active Memories

One of the biggest challenges facing modern computer architects is overcoming the memory wall Technology trends dictate that the gap between processor and memory performance is widening Even though good cache behavior mitigates this problem to some extent memory latency remains a critical performance bottleneck in modern high performance processors Al though current high speed systems have improved memory bandwidth by using heavily pipelined clocked architectures these techniques do not improve memory latency and they burden the memory controller designer with a number of complex timing constraints We propose to tackle several challenges facing modern memory system designers by study ing asynchronous active memories pipelined memory systems that do not use clocks for their operation We believe that our approach addresses the shortcomings in current designs and provides the bene ts of simple controller design average case performance and support for non uniform memory access times The latter bene t is the key to transparent support for active memories